1. Field of the Invention
The present invention relates to switched capacitor circuits and, in particular, to circuits and methods for decreasing the charge time of a switched capacitor circuit while not increasing switch induced charge injection.
2. Discussion of the Prior Art.
A typical sample and hold, switched capacitor circuit 10 is shown in FIG. 1. In the Fig. 1 circuit 10, an n-channel transistor M1 is connected between the input V.sub.IN and the output V.sub.OUT. A capacitor C.sub.S is connected between the output V.sub.OUT and ground. A control signal CONTROL drives the gate of transistor Ml.
Since transistor MI may be thought of as an equivalent resistor R.sub.eq =R(M1) for V.sub.IN &lt;V.sub.CONTROL -V.sub.tn, the switched capacitor circuit 10 shown in FIG. 1 may be illustrated as an RC circuit 10' during a sample time t.sub.s, as shown in FIG. 2.
Referring to the timing waveforms shown in FIG. 3, when the control signal CONTROL is held on for the sample time t.sub.s, the sample held output V.sub.OUT approaches V.sub.IN in an exponential fashion. The time constant is determined by the resistance R.sub.eq and the capacitance C.sub.s. At time t.sub.s, the n-channel switch M1 is turned off. Due to the charge resident in the channel of transistor M1 at turnoff and the gate/channel overlap capacitor, an offset voltage V.sub.OF is induced. The parameter t.sub.s is chosen such that, in the worst case scenario, V.sub.OUT will become equal to V.sub.IN to within a small tolerance, for example 0.1%.
The constraints of acquisition time and charge injection make opposite demands on the sample switch. A fast acquisition time requires a sample switch M1 having a large channel width/channel length ratio (W/L) for a low RC time constant with the sample capacitor. However, a large W/L ratio switch requires a physically large channel which gives it a large stored channel charge and a large overlap capacitor formed by the channel width times the gate channel overlap (W*L.sub.OVLP). This results in a larger induced offset voltage than for a smaller switch using identical charge injection cancellation techniques.
Low offset voltage, therefore, requires a small switch Ml. However, in many cases, this switch may have too high a channel resistance to charge the sample capacitor in the given acquisition time t.sub.s to the required tolerance.